领先同行瑞萨低相噪时钟振荡器应用

领先同行瑞萨低相噪时钟振荡器应用，瑞萨提供业内最广泛和最深入的硅时序产品组合。除了种类繁多的缓冲器和时钟频率合成器产品，我们还提供领先的时钟振荡器解决方案，以解决几乎任何应用中的时序挑战。我们的产品组合在模拟和数字时序领域拥有超过20年的成熟专业知识，在先进的时序技术中具有最低的相位噪声和最高的性能。

时序和时钟IC广泛应用于网络、射频、物联网、电信、图像传感器、医疗甚至音频应用。设计时序IC的外部电路时，我们必须注意电源设计。就像我们不应该给兰博基尼加满廉价的汽油一样，我们也不应该用高噪声电源给低噪声时序IC供电。

对于上述所有应用中使用的定时和时钟IC，电源通常是电池或5V至AC之间的任何电压总线。电源电压通常通过开关模式电源被逐步降低到适当的水平。这里，一些外部辐射或传导噪声可能会耦合到系统中，电源可能会产生自己的内部噪声，导致其输出电压携带较宽的频谱，并产生不准确的时序/时钟信号。如果不添加强滤波器或低噪声LDO，我们就不能直接从这种高噪声电源为任何噪声敏感的时序或时钟IC供电，如图1所示。由于SMD振荡器尺寸优势、精确的输出电压和更好的动态负载响应，低噪声LDO始终优于大型滤波器.

这种低噪声LDO通常具有非常高的电源抑制比(PSRR)来阻挡输入噪声，并且其自生噪声也非常低。PSRR是特定频率下LDO输入电压纹波与输出电压纹波的比值，通常以对数形式表示:

PSRR通常随负载电流、裕量电压、输出电容以及外部噪声滤波器电容和输出电压而变化，具体取决于有源晶振器件。外部电容可以轻松改善高频PSRR。然而，对于低频滤波，电容可能变得相当大且昂贵，因此选择在低频具有非常高PSRR的LDO可能有助于减小电容尺寸。

图2显示了不同系统设置下的PSRR方差。根据图2B，PSRR较高，高频时输出电容较大，而LDO在低频时已经有很高的PSRR。根据图2D，如果在轻负载下需要更高的PSRR，设计人员可以在带隙引脚上增加一个小的低成本电容，不仅可以改善PSRR，还可以改善内部噪声。领先同行瑞萨低相噪时钟振荡器应用.

图2 PSRR与其他系统设置

LDO的另一个重要参数是内部噪声，它以两种方式表示。一个是频谱噪声密度，这是一条显示噪声与频率关系的曲线。在射频等频谱受管制的应用中，噪声必须控制在“发射屏蔽”范围内，才能通过认证测试。因此，用户应检查目标频率附近的频谱噪声密度曲线。典型的频谱噪声图如图3所示。

瑞萨发布两款超低噪声LDORAA214020和RAA214023额定电压为5.5V，2A输出，现在完全有资格为瑞萨时序和时钟IC产品组合供电，并且包含在每个评估板的BOM中。下面给出了一些匹配时钟IC和LDO器件的例子。更多不同电流额定值和性能的低噪声LDO即将推出。

Renesas offers the broadest and deepest silicon timing portfolio in the industry. In addition to our wide selection of buffers and clock synthesizer products, we deliver leading-edge system timing solutions to resolve timing challenges in virtually any application. With proven expertise spanning more than twenty years in both analog and digital timing, our portfolio features the lowest phase noise and highest performance in advanced timing technology.

The timing and clock ICs are widely used in applications like networking, RF, IoT, telecom, image sensors, medical, and even audio applications. When designing the external circuitry around a timing IC, we must pay attention to the power supply design. Just like we should not fill a Lamborghini with cheap gas, we are not supposed to power our low-noise timing ICs with noisy power supplies.

For timing and clock ICs used in all the mentioned applications, the power source is usually either battery or any voltage bus between 5V to AC. The power source voltage is typically stepped down to an appropriate level through a switch-mode power supply. Here, some external radiated or conducted noise may be coupled into the system and the power supply may generate its own internal noise causing its output voltage to carry a wide frequency spectrum and inaccurate timing/clock signals to be generated. We should not feed any noise-sensitive timing or clock IC directly from such noisy power supply without adding a strong filter or a low-noise LDO, as shown in Figure 1. A low-noise LDO is always preferred over large filters due to size advantage, accurate output voltage and better dynamic load response.

Such low-noise LDO often has very high Power Supply Rejection Ratio (PSRR) to block the incoming noise and it has very low self-generated noise as well. The PSRR is the ratio LDO input voltage ripple vs. output voltage ripple at a specific frequency, and is typically expressed in log form:

The PSRR typically varies with load current, headroom voltage, output capacitor, and, depending on the part, external noise filter capacitor and output voltage. High-frequency PSRR can be easily improved by external capacitors. However, for low-frequency filtering, the capacitor may become quite large and expensive, therefore selecting an LDO with very high PSRR at low frequencies may help reduce the capacitor size.

Figure 2 shows the PSRR variance over various system settings. Per Figure 2B, the PSRR is higher with a larger output capacitor at high frequencies and the LDO already has very high PSRR at low frequencies. Per Figure 2D, if an even higher PSRR at light load is desired, a designer can add a small, low-cost capacitor on the bandgap pin, which improves not only PSRR, but the internal noise as well.

The other important parameter with an LDO is the internal noise, which is indicated in two fashions. One is spectral noise density, a curve that shows noise versus frequency. In applications like RF with regulation on the frequency spectrum, the noise has to be controlled within the “transmit mask” to pass certification testing. Hence, the user should check Spectral Noise Density curves around the frequency of interest. A typical spectral noise chart is shown in Figure 3.

The other is integrated output noise, also commonly called output noise voltage. It is the spectral noise density integrated over a certain frequency range. In applications like ADC or DAC, all the LDO noise from DC to the bandwidth of the system is integrated and computed as a whole to affect the ADC/DAC accuracy. Therefore, total output noise is important for such applications, and a typical chart is shown in Figure 4. Figure 3 and 4 are taken from Renesas low noise LDOs with excellent performance.